Integrated circuits require a clocking scheme in order to execute instructions and transfer data between functional blocks on the integrated circuit in a synchronised manner. The aim of conventional integrated circuits is for the clock signals to arrive at every circuit element or module simultaneously, so that the circuit elements operate in synchronism. Integrated circuits are therefore typically designed so that the clock signal is distributed in a symmetrical manner across the chip from a centrally located clock reference.
Despite the symmetry associated with prior art clock distribution schemes, imperfections in circuit conductors and variations introduced in the manufacturing process introduce clock skew between circuit elements or modules.
Existing development tools for designing integrated circuits have an automated process for distributing a balanced clock across a chip, so that each of the functional units on the chip operate in synchronism. The automated process for balancing the clock involves a two-stage process. Firstly, a clock tree is inserted into each functional block. Each block has a different insertion delay. Once the functional blocks are placed on the layout floorplan, the second stage of the process involves balancing the clock tree in order to reduce clock skew to within acceptable limits. This involves inserting additional buffers in each path to balance the skew at all clock inputs to every register on the chip. Using this technique the clock tree can be balanced to within 200-300 ps.
The conventional process described above has a number of drawbacks. For example, although the task of inserting the clock buffers into each path to the functional units is relatively automated, the second stage of the process requires more manual intervention, i.e. the tools must be directed as to where the additional clock buffers are to be inserted. This process is time consuming and it is difficult to determine whether the clock skew is within the acceptable tolerance levels. The constant desire to increase clock frequencies means that the problems mentioned above become even more relevant. As a consequence, it becomes difficult to simulate a large integrated circuit within a reasonable time-frame.
The balanced clock tree described above is a standard part of synchronous design methodology. However, a further disadvantage of this technique is that all registers across the whole chip are updated by the arrival of the clock edge, which results in a massive spike in the current drawn by the chip. This current surge is undesirable from a number of viewpoints. For example, the current surges cause unwanted electromagnetic emissions and can also lead to reliability problems due to electromigration failures.
A further disadvantage is that the track sizes have to be larger than necessary to deal with the large current surges. In addition, areas of silicon must be left unused so that the top-level clock drivers can be inserted.
The aim of the present invention is to provide a clock distribution system for an integrated circuit which is tolerable to clock skew, and which simplifies the process of designing large integrated circuits.